An analog-to-digital converter for processing an analog band-pass signal, to yield a digital base band signal needs to perform two principal tasks: down-conversion (frequency translation) and analog-to-digital conversion. The band-pass signal can be a one of a band-pass signal or an intermediate frequency signal. Many known receivers perform the down-conversion (or at least a significant part of the down-conversion) in the analog domain using analog circuitry. More recent receivers tend to shift the analog-to-digital conversion towards the intermediate frequency or the radio frequency (RF) front end. This development has been made possible by advances in the technology of analog-to-digital converters.
One of the types of analog-to-digital converters that has been found to be suitable for the processing of analog intermediate frequency or RF signals is a delta-sigma modulator type of analog-to-digital converters. The article “Excess Loop Delay Effects in Continuous-Time Delta-Sigma Modulators and the Compensation Solution”, Weinan Gao et. all, 1997 IEEE International Symposium on Circuits and Systems, Jun. 9-12, 1997, Hong Kong (hereafter referred to as “GAO”) describes a receiver/analog-to-digital converter with a band-pass delta-sigma modulator (BPDSM). The band-pass delta-sigma modulator is clocked at 3.6 GHz and is used to receive a 900 MHz RF analog signal, i.e. the clock frequency of the delta-sigma modulator is four times higher than the frequency of the received RF analog signal. This so called 4:1 mode is often used for analog-to-digital converters, because samples from the analog signal can be taken at RF carrier phases of 0°, 90°, 180°, and 270°. The corresponding sampling instances are +I, +Q, −I, −Q samples. Another common frequency ratio is 4:3, where the samples are taken at RF carrier phases of 0°, 270°, 180°, and 90° (i.e. sampling instances are +I, −Q, −I, +Q).
It would be desirable to provide for an analog-to-digital converter (ADC) that allows for a high dynamic range. It would be further desirable to provide for an ADC with low power consumption. It would be further desirable to provide for an ADC with high image rejection.